The invention relates generally to memory control devices and methods and more particularly to screen display FIFO memory management systems and methods. One of the recent trends in high performance graphics chip design requires support of graphic display modes with high resolutions (up to 1600xc3x971200), high screen refresh rates (up to 200 Hz), and high color depth (24 bit or 32 bit true color). The combination of high resolution, high refresh rates and high color depth requires a very high memory bandwidth to perform proper screen refreshes. A display mode of 1152xc3x97864xc3x9732 bpp@75 Hz, for example, requires a memory bandwidth of 440 Mb/s for screen refreshes. To meet such a high memory bandwidth requirement, new high performance memories like SDRAM""s are typically required for frame buffer memory. Equally important is the design of high performance memory controllers that can take advantage of the high performance of such new memories.
A display FIFO memory (buffer) is usually implemented in graphics chips to buffer the data for screen refreshes. The role of this display FIFO memory is two-fold. The first is to sustain a long burst read of display data from the frame buffer memory, so that a high memory read efficiency can be achieved, and the second is to allow the screen refresh unit to tolerate memory access latencies while the memory controller services other requests from requesters in the graphics chip, such as the GUI engine for example. The display FIFO memory in a graphics chip is usually made up of a SRAM macro cell of 8 to 32 entries with each entry 32 or 64 bits wide. The display FIFO is a precious resource in a graphics chip since it can occupy a significant amount of chip area. Hence there is a continuing need for memory controllers that can use minimum amounts of the display FIFO memory entries while also supporting required high bandwidth display modes.
Displays must receive screen refresh data in real time to avoid loss of screen resolution. The screen refresh unit therefore generates a real time refresh request from the memory controller. With higher resolution display modes, it is important to meet the requirement of both the memory bandwidth and an allowable memory access latency period.
Generally, filling and draining of display FIFO memory entries occurs at the same time. The display receives the refresh data in bursts to free up the memory for use by other requests in hardware. A FIFO controller typically determines how man entries remain in the FIFO memory and how many entries to fill to facilitate proper refresh of the display.
However, the display FIFO memory read rates and writes rates are different resulting in two clock domains. The read rate to drain the display FIFO memory is based on the video clock rate (VCLK) at which the display screen requires refresh data. Reading data from the display FIFO to the screen can be on the order of 100 Mb/sec. In contrast, the write rate to fill the display FIFO is based on the memory clock (XCLK) since the memory clock is used to retrieve data from memory. Display FIFO memory write or fill rates can be 800 Mb/sec so that the FIFO memory entries are filled faster than they are drained.
In conventional memory controllers, display FIFO memory management systems perform a conversion of the two different clock domains by analyzing the location of the read and write pointers of the FIFO memory to determine how many entries have been drained. The read pointer keeps track of how much data has been read from the FIFO memory by the screen refresh unit. The write pointer keeps track of how many entries of data have been filled in the FIFO memory by the memory controller. A comparator is used to compare the read and write pointers to determine how many FIFO memory entries are left over in the FIFO memory at any given time. When the difference between the two pointers is greater than a pre-defined value, a so called low watermark, the FIFO control circuitry start to generate requests to the memory controller to request more data to fill the FIFO memory, As the FIFO memory fills, the difference between the read and write pointer becomes smaller and smaller. When the difference between the read and write pointer become zero, the FIFO is full, and FIFO control circuitry stops requesting data from memory controller.
One major shortcoming of the conventional FIFO memory management scheme is that it can not make use of every entry of the display FIFO memory. For example, re-synchronization can waste up to 2 entries. Since the read and write pointers are on two different clock domains, (the read pointer is in the screen refresh clock (VCLK) domain, and the write pointer is in the memory clock (XCLK) domain) one of the pointers has to be brought across the clock boundary to the other clock domain in order to compare them. It can take one clock cycle to make the conversion resulting, in a re-synchronization error. To avoid an underflow condition, an extra entry is typically added to the low watermark to compensate for the one clock re-synchronization uncertainty. Also because of this uncertainty, the FIFO memory full point is also typically lowered by one entry in order to prevent FIFO memory overflow.
Moreover, high performance memory controllers usually use pipeline designs to increase memory interface speed. A three stage pipeline memory controller needs three clock cycles to process a FIFO memory fill request. The latency between the memory, controller accepting a request and data coming back can cost up to three entries in the display FIFO memory. This is because the write pointer is incremented according to the ready signal sent back by the memory controller, and when the comparator shows that the FIFO memory is full and turns off the request, the last piece of data does not come back until three clocks later, during which time the FIFO memory has already drained several entries. Therefore, the FIFO memory is never actually filled to capacity at any time. The actual number of entries that are wasted due to the FIFO memory never filling to capacity depends on the memory type and screen display modes. The higher the display bandwidth requirement, the more entries that are typically wasted. Also an SDRAM generally wastes more entries than a DRAM, because an SDRAM fills at a rate of one entry per clock cycle. In the case of a very with bandwidth display mode the drain rate is almost equal to the fill rate, so the drain rate is also close to one. Consequently every clock latency can waste an entry in FIFO memory. In conventional display FIFO management systems, the FIFO is typically made larger to compensate for the error by allowing more space for overflow to occur. Unnecessarily increasing the size of the display FIFO uses up valuable chip area and increases the cost of the graphics system.
In addition, the wasting of display FIFO memory entries can hurt the performance of a graphics chip. First the loss of FIFO memory entries makes the burst reading length shorter for the filling of the display FIFO memory. The shorter burst reading length lowers the efficiency of memory bandwidth usage for a screen refresh. The lowering in memory bandwidth usable often means the screen refresh operation needs more row memory bandwidth than ordinarily required to support the same display mode. Therefore, other functions of the graphics chip like the GUI engine, the video capture function and other functions, receive less memory bandwidth, so that the performance of the graphics chip as a whole decreases. Second, the shrinking of the effective display FIFO memory reduces its ability to tolerate memory, access latencies. This has the most profound effect at high bandwidth display modes since, the full size of display FIFO memory is typically marginally large enough to tolerate the memory access latency period. Any wasting of display FIFO memory entries can risk losing the support of higher resolution display modes. Consequently, there exists a need for an improved display FIFO memory management system that substantially overcomes one or more of the above problems.